1. Field of the Invention
The present invention relates to a silicon carbide semiconductor device including a deep layer.
2. Description of the Related Art
A silicon carbide (SiC) semiconductor device typically has a high breakdown field strength and can therefore control a high current. The SiC semiconductor device can be used for controlling a motor of a hybrid vehicle, for example.
In order to increase electric current that flows in a semiconductor device, a channel density can be increased. In a silicon semiconductor device, a metal-oxide semiconductor field-effect transistor (MOSFET) having a trench gate structure is in practical use. When a trench gate structure is applied to the SiC semiconductor device, difficulty arises. The breakdown field strength of SiC is about ten times greater than a breakdown field strength of silicon. Thus, a voltage about ten times greater than a voltage applied to the silicon semiconductor device may be applied to the SiC semiconductor device. If such a voltage is applied, a gate insulating layer disposed in a plurality of trenches provided in an SiC substrate may receive an electric field about ten times greater than an electric field in the silicon semiconductor device. As a result, the gate insulating layer may be damaged, for example, at a corner portion of each of the trenches. According to a simulation by the inventors named in the present application, when a voltage of about 650 V is applied to a drain, the gate insulating layer in the trenches receives an electric field of about 4.9 MV/cm. The electric filed applied to the gate insulating layer is required to be about 3 MV/cm or less for practical use. Furthermore, the electric filed applied to the gate insulating layer is required to be  about 2 MV/cm or less for long-term use.
In an SiC semiconductor device described in U.S. Pat. No. 5,744,826 (corresponding to JP-A-9-199724), a thickness of an gate insulating layer located at a bottom portion of each of the trenches is set to be greater than a thickness of the gate insulating layer located at a sidewall of each of the trenches for reducing an electric field concentration at the bottom portion of each of the trenches. The SiC semiconductor device described in U.S. Pat. No. 5,744,826 is made of a 4H-SiC substrate having a main surface of (000-1)-face and the trenches extend in a (1120)-direction. An oxidation rate of the (000-1)-face is about five times greater than an oxidation rate of the (1120)-face. Thus, when a gate insulation layer is formed by thermal oxidation in the trenches that have a sidewall of (1120)-face and a bottom of (000-1)-face, a thickness of an oxide layer formed at the bottom portion can be about five times greater than a thickness of the oxide layer formed on the sidewall. Thereby, the electric field concentration at the bottom portion of the trenches can be reduced.
According to another simulation by the inventors, in which a thickness of the gate insulating layer on the sidewall is set to be about 40 nm and the thickness of gate insulation layer at the bottom portion is set to be about 200 nm, when a voltage of about 650 V is applied to a drain, the electric field concentration at the gate insulating layer in the trenches can be reduced to about 3.9 MV/cm. However, further relaxation of the electric field is required.
U.S. patent application Ser. No. 12/289,624 filed on Oct. 29, 2008 (corresponding to Japanese Patent Application No. 2007-288545) and made by one of the present inventers describes an SiC semiconductor device including P type deep layers formed along a longitudinal direction of a trench gate. The P type deep layers are located on an opposite side of an N+ type source region and a P type base region from the trench gate. The P type deep layers are located under a P+ type contact region for electrically coupling the P type base region and a source electrode. The P type deep layers extend to a depth deeper than a bottom portion of the trench gate. In the SiC semiconductor device described therein, the electric field can be further relaxed.
In a manufacturing process of the above-described SiC semiconductor device, the trench gate and the P type deep layers are formed during different  processes. Thus, a positioning is difficult, and a distance between a sidewall of the trench and the P type deep layer may vary. As a result, a production property may vary and a yield may be reduced.
Japanese Patent Application No. 2008-31704 made by one of the present inventers describes an SiC semiconductor device including P type deep layers formed along an approximately normal direction of a sidewall of a trench where a channel region is provided. In such a configuration, a depletion layer expands toward an N− type drift layer at a PN junction between P type deep layers and the N− type drift layer. Thus, a high voltage due to a drain voltage is restricted from being applied to a gate oxide layer. Thereby, an electric field concentration in the gate oxide layer, especially, an electric field concentration in the gate oxide layer at a bottom portion of the trench can be reduced. In addition, a longitudinal direction of the trench and a longitudinal direction of the deep layers are approximately perpendicular to each other. Thus, a device property is not affected by a misalignment of masks.
In the above-described configuration, the P type deep layers are arranged parallel to each other in a stripe pattern. Thus, the P type deep layers are separated from each other. When a breakdown occurs, electric current may concentrates in one of the P type deep layers. Thus, an imbalance of the electric current may occur and an element may be damaged due to an electric current concentration.